The present invention relates to optoelectronic devices, electrodes for introducing current to optoelectronic devices, and methods of making optoelectronic devices and electrodes for the same.
Optoelectronic devices typically include a semiconductor structure arranged for generating light when a current is introduced through the structure. Optoelectronic devices typically have semiconductor structures incorporating thin layers of semiconductor materials exhibiting opposite conductivity types, referred to as p-type conductivity and n-type conductivity. The p-type and n-type semiconductor layers are typically disposed in a stack, one above the other so as to form a junction with one another. In certain structures, the p-type layer is disposed at the top of the stack of semiconductor layers and the n-type layer is disposed at the bottom of the stack. As used herein, references to the top or bottom of any feature are to be taken with reference to the device itself, as opposed to any gravitational frame of reference, as the devices disclosed herein could be oriented in any direction. The junction between the p-type and n-type material may include directly abutting p-type and n-type layers, or may include one or more intermediate layers which may be of any conductivity type or which may have no distinct conductivity type. The junction may also include other structures.
Light is generated at the junction when an electric current is introduced to the structure. As used in this disclosure, the term xe2x80x9clightxe2x80x9d includes radiation in the infrared and ultraviolet wavelength range, as well as the visible range. The wavelength of the light depends on factors including the composition of the semiconductor materials and the structure of the junction. One electrode is mounted on the p-type layer and another electrode is mounted near or on the n-type layer so as to introduce a current through those layers and through the junction. The materials in the electrode are selected to form low-resistance interfaces with the semiconductor materials. The electrodes may include pads for forming connections with other conductors for carrying current from external sources. The term xe2x80x9celectrode-pad unitxe2x80x9d as used in this disclosure refers to the electrode and the pad, whether the pad is a separate structure or formed as part of the electrode, or comprises a region of the electrode.
Certain structures incorporate current-spreading electrodes. Current-spreading electrodes make broad contact with the semiconductor structure and cover a significant portion of the top surface of the stack. Such electrodes spread the current delivered to the top surface of the stack so that the effects of so-called xe2x80x9ccurrent bunchingxe2x80x9d or xe2x80x9ccurrent crowdingxe2x80x9d are reduced. Current bunching is the tendency for current to travel straight through the semiconductor structure in a downward direction. Current is concentrated in that portion of the junction beneath the electrode. The light is generated in only the region accessed by the current. Where the electrode covers only a relatively small portion of the top surface of the stack, the amount of useful light reaching the outside of the optoelectronic structure per unit of electrical current passing through the structure, commonly referred to the external quantum efficiency of the structure, is reduced by current bunching. Thus, it is desirable to spread the current introduced to the semiconductor structure. In certain devices, a current-spreading electrode is often placed on a major surface of the device. Conductive materials utilized for electrodes in many contexts typically comprise metals that are opaque to light. Since a current-spreading electrode covers a major surface of the structure, the light generated by the structure does not pass through this surface if an opaque metal electrode is used. In certain applications, it is desirable to utilize a transparent electrode, so that the light can pass through the transparent electrode.
Certain optoelectronic devices, such as light-emitting diodes (LEDs), are formed with a region of the semiconductor structure removed so that an upwardly facing lower region is formed and an upwardly protruding region, referred to as a mesa, is formed. The top of the mesa typically comprises the top of a p-type semiconductor material on which a top electrode is disposed. A lower electrode is formed on the lower region, near the n-type layer. This structure is typically formed on a substrate or is otherwise mounted to a substrate or other support beneath the n-type layer so that light is directed out the top of the structure. Reflectors may be included in the support or within the semiconductor structure itself to direct light upwardly. In these structures, it is desirable that the top electrode is comprised of a substantially transparent material so that at least a portion of the light emitted by the LED shines out the top of the structure, in addition to the sides. It is preferred that the top electrode is as transparent to the light generated as possible.
In forming an optoelectronic device having a mesa, the mesa is typically formed first and then the p-type electrode is formed on the mesa. A first resist is applied to the structure and photolithographically patterned to form openings over certain regions of the structure. After patterning, the first resist remains on those regions of the wafer corresponding to the areas where mesas are to be formed. The regions of the semiconductor structure that are aligned with the openings in the first resist are removed by etching. The regions covered by the resist remain as mesas, which protrude from the structure. The first resist is stripped and a second resist is applied to the structure, and patterned to form openings for the p-type electrodes on the top of the mesas. Metal is then deposited in these openings. The metal deposited on the top of the mesa may be comprised of one or more metals that are selected to form a transparent electrode, upon subsequent annealing of the metals.
The inventors have found that the foregoing process interferes with the optimum development of a transparent electrode. Without committing to any theory of operation, it is believed that the use of the resist layers on the top of the semiconductor structure interferes with achieving transparency after annealing. In addition, the second resist must be carefully registered with the mesas to avoid malformed p-type electrodes. If an opening in the second resist extends over an edge of a mesa due to misregistration, the resulting top electrode will contact the lower electrode on the lower region, thus shorting out the device. It is preferred that the top electrode is as transparent to the light generated as possible. It is also desirable to form the top electrode so that the edges of the electrode are spaced from the edges of the mesa, also to avoid shorting out the device.
Improvements in the methods of forming electrodes on semiconductor structures to address the foregoing issues are desirable.
The present invention addresses these needs.
The method of making an electrode on a semiconductor structure comprises depositing metal on a surface of a semiconductor structure and forming a patterned mask over the metal on the semiconductor structure. The mask has at least one opening so that a first region is covered by the mask and a second region aligned with the at least one opening in the mask is left uncovered by the mask. The method also includes removing metal aligned with the at least one opening of the mask in the second region so as to reveal the surface of the semiconductor structure in the second region, and removing material from the semiconductor structure aligned with the at least one opening in the second region. Thus, the same mask is utilized in forming the electrode on the semiconductor structure and also used in removing material from the semiconductor structure. In removing material from the semiconductor structure, an upwardly protruding portion of the semiconductor structure is formed. The major surface of the protruding portion has metal for an electrode disposed thereon. Methods according to embodiments of the invention avoid the extra step of utilizing a separate mask in depositing metal on the structure. In addition, methods according to embodiments of the invention can be used to form an electrode registered with the upwardly protruding portion and spaced from the edge thereof. The registration of the metal on the upwardly protruding portion of the structure can avoid shorting of the device comprising the semiconductor structure.
In certain preferred embodiments, the metal comprises a first metal and a second metal. The method may include annealing the first metal and the second metal. The first metal and second metal are desirably selected to form a substantially transparent material upon annealing. In certain preferred embodiments, the first metal comprises nickel and the second metal comprises gold. The step of depositing the metal may comprise electron beam deposition. The first metal and second metal may be deposited as separate layers by depositing a first metal and then depositing a second metal overlying the first metal. Thus, an electrode may be formed on top of the upwardly protruding portion of the semiconductor structure and the electrode may be comprised of one or more metals or layers of one or more metals.
In certain embodiments, the step of forming a patterned mask comprises applying a resist on the deposited metal and lithographically patterning the resist to form openings over the second region. The remaining resist overlies the semiconductor structure in the first region.
Desirably, the steps of removing metal and removing material from the semiconductor structure comprise etching. The step of removing metal may comprise, for example, etching with a KI:I2:DI solution. The step of removing material from the semiconductor structure desirably comprises etching the semiconductor structure while the resist remains over the semiconductor structure in the first region. The step of removing material from the semiconductor structure desirably comprises a reactive ion etching (xe2x80x9cRIExe2x80x9d). The step of etching may also comprise etching with BCl3.
The resist layer covering the first region may have edges and the step of removing metal may be performed so as to remove some of the metal underneath the resist layer, adjacent the edges of the resist layer, to form a space between the edges of the resist layer and the metal on the semiconductor structure. The metal in the first region preferably substantially covers the first region, except in the space between the edges of the resist layer and the metal. Thus, the metal in the first region is spaced from the edges of the resist layer. When the upwardly protruding portion of the semiconductor structure is formed, the resist layer substantially protects the semiconductor structure in the first region, directly beneath the resist layer, and the portion of the semiconductor in the second region is removed. The metal in the first region is spaced from the edges of the protruding portion. Shorting of the device formed from the semiconductor structure is largely avoided where the metal is formed so that the metal is spaced from the edge of the protruding portion.
The step of removing material from the semiconductor structure in the second region is preferably performed so as to leave the first region protruding from the remainder of the semiconductor structure. The semiconductor structure comprises a p-type semiconductor layer overlying an n-type semiconductor layer arranged beneath the p-type semiconductor layer. The semiconductor structure has a junction between the p-type and the n-type layer. Thus, when the upwardly protruding portion of the semiconductor structure is formed, the upwardly protruding portion comprises a portion of the p-type layer and a lower region is formed, which comprises a portion of the n-type layer. Desirably, when the upwardly protruding portion is formed, the metal covers a large portion of the semiconductor structure in the first region and the metal is in contact with the p-type layer.
The method also preferably includes forming a lower electrode on the n-type layer of the lower region.
In another aspect of the present invention, a method of making a transparent electrode for a light-emitting diode comprises depositing metal on a top surface of the semiconductor structure, defining a first region of the semiconductor structure for a first electrode by forming a mask over the metal. The mask has an opening so that the first region is covered by the mask and a second region is aligned with the opening of the mask. The method also comprises removing metal aligned with the opening of the mask in the second region, so as to reveal the top surface of the semiconductor structure in the second region, and removing material from the semiconductor structure aligned with the opening in the second region to form a second electrode surface for a second electrode. The second electrode surface is lower in elevation than the top surface of the semiconductor structure. In certain preferred embodiments, the method is utilized to form a light-emitting diode having an upwardly protruding mesa and the metal deposited forms a first electrode on the mesa.
The method may also comprise the step of depositing metal, including depositing a first metal and depositing a second metal. In certain preferred embodiments, the first metal and second metal are annealed. The first metal and second metal may be selected to form a substantially transparent material upon annealing. The first metal preferably comprises nickel and the second metal preferably comprises gold. The step of depositing may comprise electron beam deposition, for example. The step of depositing metal may comprise depositing a first metal and depositing a second metal overlying the first metal. Thus, the metal may be deposited as separate layers.
In certain preferred embodiments, the step of defining a first region comprises applying a resist on the metal and lithographically patterning the resist to form openings in the second region so that the remaining resist overlies the semiconductor structure in the first region.
The step of removing metal and the step of removing material from the semiconductor structure may comprise etching. The step of etching to remove metal may be performed with a KI:I2:DI solution. The step of removing material from the semiconductor structure desirably comprises etching the semiconductor structure while the resist remains in the first region. Etching the semiconductor structure may comprise reactive ion etching (xe2x80x9cRIExe2x80x9d). Etching the semiconductor structure may also comprise etching with BCl3.
The resist layer in the first region may have edges and the step of removing metal may be performed so as remove some of the metal underneath the resist layer, adjacent the edges of the resist layer, to form a space between the edges of the resist layer and the metal on the semiconductor structure. The metal in the first region preferably substantially covers the first region, except in the space between the edges of the resist layer and the metal on the semiconductor structure. The step of removing material from the semiconductor structure may be performed so as to leave the first region protruding from the remainder of the semiconductor structure.
The semiconductor structure may comprise a p-type semiconductor layer overlying an n-type semiconductor layer arranged beneath the p-type semiconductor layer. The semiconductor structure may have a junction between the p-type layer and the n-type layer. The step of removing material from the semiconductor structure preferably forms an upwardly protruding portion of the p-type layer and a lower region, preferably comprising a portion of the n-type layer. Desirably, the first region forms the mesa of the light-emitting diode, and the metal forms an electrode on the mesa. The metal preferably covers a large portion of the semiconductor structure in the first region and is in contact with the p-type layer.
Preferably, the method further includes forming a lower electrode on the n-type layer of the lower region.